logic analyzer waveform loading

while troublshooting a SPI bus problem (SPI bus speed about 900Khz), I noticed that the bus signals while the analog probes were connected were square-good rise/fall times. But after additionally connecting a digital input (this is what I wanted to troubleshoot the problem with) the waveforms became rounded (as seen on the analog trace), almost like a sinewave. I disconnected the digital input at the CAU (leaving the digital probe connected)and the waveform returned to normal. I plugged the digital input back into the CAU and disconnected the analog probe to remove its loading effects, the SPI bus would not run. What is the input capacitance of the digital inputs at the CAU? Any ideas?

while troublshooting a SPI bus problem (SPI bus speed about 900Khz), I noticed that the bus signals while the analog probes were connected were square-good rise/fall times. But after additionally connecting a digital input (this is what I wanted to troubleshoot the problem with) the waveforms became rounded (as seen on the analog trace), almost like a sinewave. I disconnected the digital input at the CAU (leaving the digital probe connected)and the waveform returned to normal. I plugged the digital input back into the CAU and disconnected the analog probe to remove its loading effects, the SPI bus would not run. What is the input capacitance of the digital inputs at the CAU? Any ideas?

Hello Dimensions,
We would not have expected loading effects. The digital inputs have the following input topology:
Low capacitance probe (< 1pf) - 270 ohm series resistor - 22p + 18p capacitive divider in parallel with 75k + 27k resistive divider - low capacitance Cat 5E twisted pair cable, low capacitance LVDS receiver (5pF maximum loading).

You can measure the input capacitance yourself using the Gain/Phase Spectrum display. Use a series resistor of some kohm (we used 12 kohm) as the known input impedance (Ri). Put the sig gen output, and Chan A to one side of the 12k. Connect Chan B to the other side of the 12k, and also the digital input. Connect all grounds together. We used approx 4V p-p out of the sig gen at 1 MHz, with both A chan and B chan probes set to 10x to minimize capacitance. It's probably a good idea to check the gain with Chan A and Chan B connected together first. If the gain is not 1.000, you can normalize it using Maths, and set the Spectrum display source to Maths. (Eg A -> A, B*0.9834 ->B).

We found with this setup, G = 0.3118, Phase angle = -66.8 degrees. So we have a capacitive component.
Solving Zx = Ri x G/(1-G), we find Zx = 5.43K. Zx is the parallel combination of Cx and Rx. Use a multimeter to measure Rx. We measured 91K. So from Zx = ZcZr/Zc+Zr, we find Zc = ZxZr/Zr-Zx. So Zc = 5.77k.

We know C = 1/2 pi F Zc = 27 pF. The input impedance is 27 pF. According to the scope probe data sheet (comes with the probe), the scope probe capacitance is 17 pF (10x setting). The capacitance is the parallel combination of the scope probe and the digital input capacitance, which is an additive sum. So the digital input capacitance is 27 - 17 = 10 pF. This is in keeping with a series combination of 22p and 18p, and confirms our design.

So is there something else going on here. Maybe you need to pay attention to grounding - if the grounds are not all common you may be driving current around, which cause the SPI driver to go into current limit, limiting slew rate. Please check this.

Hello Dimensions, We would not have expected loading effects. The digital inputs have the following input topology: Low capacitance probe (< 1pf) - 270 ohm series resistor - 22p + 18p capacitive divider in parallel with 75k + 27k resistive divider - low capacitance Cat 5E twisted pair cable, low capacitance LVDS receiver (5pF maximum loading). You can measure the input capacitance yourself using the Gain/Phase Spectrum display. Use a series resistor of some kohm (we used 12 kohm) as the known input impedance (Ri). Put the sig gen output, and Chan A to one side of the 12k. Connect Chan B to the other side of the 12k, and also the digital input. Connect all grounds together. We used approx 4V p-p out of the sig gen at 1 MHz, with both A chan and B chan probes set to 10x to minimize capacitance. It's probably a good idea to check the gain with Chan A and Chan B connected together first. If the gain is not 1.000, you can normalize it using Maths, and set the Spectrum display source to Maths. (Eg A -> A, B*0.9834 ->B). We found with this setup, G = 0.3118, Phase angle = -66.8 degrees. So we have a capacitive component. Solving Zx = Ri x G/(1-G), we find Zx = 5.43K. Zx is the parallel combination of Cx and Rx. Use a multimeter to measure Rx. We measured 91K. So from Zx = ZcZr/Zc+Zr, we find Zc = ZxZr/Zr-Zx. So Zc = 5.77k. We know C = 1/2 pi F Zc = 27 pF. The input impedance is 27 pF. According to the scope probe data sheet (comes with the probe), the scope probe capacitance is 17 pF (10x setting). The capacitance is the parallel combination of the scope probe and the digital input capacitance, which is an additive sum. So the digital input capacitance is 27 - 17 = 10 pF. This is in keeping with a series combination of 22p and 18p, and confirms our design. So is there something else going on here. Maybe you need to pay attention to grounding - if the grounds are not all common you may be driving current around, which cause the SPI driver to go into current limit, limiting slew rate. Please check this.