Sig. gen. below 0.5V

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28 Jul 2007

I downloaded v4.614 into my CS328A and the sig. gen. works much better now however the output does not go below 0.5V.
Is this some kind of hardware limitation or something else?

If this is the way it suppose to work, then the sig. gen. slider should not go below 0.5 to properly represent the signal.
I usually do not check the signal and assume the sliders are correct.

28 Jul 2007
Posts: 396

You are quite right. It is a hardware limitation. We will fix the slider.

31 Jul 2007

That will take care of my issue.
You should also fix the specification (web, manual) where the output range is sometimes 0-5Vp-p or 0.1-5Vp-p.

Another question is: how do you use FSK and PSK synchronization? I do not recall seeing it explained anywhere.

31 Jul 2007
Posts: 396

Ok about the spec.
FSK/PSK. The answer is we have the capability in the acquisition unit, but not built a GUI for it, because no one asked (not one, in all this time). Our thinking is that there should be extra entries in the acquisition settings:

1. Frequency offset - this is the offset frequency from the current output frequency that is the alternate frequency.
2. Phase offset - this is phase offset from the current phase
3. Input used to key - In1 - 8, and Ext Trig.
4. Normal, FSK, PSK enable.

Then you attach the keying signal to the digital input chosen, and the output will toggle between the two frequecies, or two phases.

How does that sound?

19 Aug 2007

It sounds OK.
I am not sure if it makes sense or if it is useful but how about using multiple inputs to trigger multiple FSK/PSK freq/phases with some kind of priority scheme?
If it is doable then it should be fairly simple.
Just an idea.
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