# DAC option impact on impedance measurements

**DAC option impact on impedance measurements**, a forum discussion on Cleverscope. Join us for more discussions on

*DAC option impact on impedance measurements*on our Questions forum.

Back to Forum Index : Back to Questions |

I'm still considering a CS320-FRA. I'm specifically interested in impedance measurement from 1mOhm to say 10 Ohms, most likely with the CS701. Reason suggests that the DAC option chosen has an impact on the low-impedance measurement resolution, i.e. more bits has greater dynamic range, and therefore resolves lower impedances and in greater detail. Are these differences documented or described anywhere? What range/resolution can one expect to achieve with the various DAC choices?

Thanks much.

Thanks much.

We have spent quite a bit of time trying to get to grips with low impedance measurement - specifically of low esr ceramic capacitors at higher frequencies.

There are two aspects to low impedance measurement - test jig parasitics, and as you say dynamic range of the ADC.

The CS320A-FRA uses a 10 bit ADC with a very good 0.1 LSB differential non linearity (DNL). This means the dynamic range gain offered by the FFT approach we use (which effectively averages results over many samples) reduces the need for a higher resolution ADC - especially at lower frequencies. At high frequencies, where the FFT is smaller, the 14 bit ADC gives best resolution.

But back to parasitics. At higher frequencies (>1 MHz) these become a real burden for measuring mOhm values. Even using 4 wire measurement (which we do), around 1mm of track between the 4 wire connection point and the DUT roughly equates to around 1nH of inductance, which at 1MHz has an impedance of 6 mOhm. At 10 Mhz it is 60 mOhm. This is larger than a good ceramic cap, and also causes resonances which aren't real.

So if you are using the FRA at below about 100 kHz, you can make measurements down to 1 mOhm without too much difficulty. 10 bit or 14 bit will both be fine. Above 100 kHz there are increasing parasitic errors which are variable due to component connection location (+/-0.5mm means big errors), which we have not as yet been able to compensate for. Currently we say you can measure down to about 10 mOhm at 1 Mhz, and 100 mOhm at 10 Mhz because of this.

We will update this when we come up with a better jig!

There are two aspects to low impedance measurement - test jig parasitics, and as you say dynamic range of the ADC.

The CS320A-FRA uses a 10 bit ADC with a very good 0.1 LSB differential non linearity (DNL). This means the dynamic range gain offered by the FFT approach we use (which effectively averages results over many samples) reduces the need for a higher resolution ADC - especially at lower frequencies. At high frequencies, where the FFT is smaller, the 14 bit ADC gives best resolution.

But back to parasitics. At higher frequencies (>1 MHz) these become a real burden for measuring mOhm values. Even using 4 wire measurement (which we do), around 1mm of track between the 4 wire connection point and the DUT roughly equates to around 1nH of inductance, which at 1MHz has an impedance of 6 mOhm. At 10 Mhz it is 60 mOhm. This is larger than a good ceramic cap, and also causes resonances which aren't real.

So if you are using the FRA at below about 100 kHz, you can make measurements down to 1 mOhm without too much difficulty. 10 bit or 14 bit will both be fine. Above 100 kHz there are increasing parasitic errors which are variable due to component connection location (+/-0.5mm means big errors), which we have not as yet been able to compensate for. Currently we say you can measure down to about 10 mOhm at 1 Mhz, and 100 mOhm at 10 Mhz because of this.

We will update this when we come up with a better jig!

Back to Forum Index : Back to Questions |