Download the CS1090 half bridge document for an example of measuring slewing gate drives (below).
Each channel is isolated from the other, and ground, to 2kV working voltage. The common mode rejection ratio is >100 dB at 50 MHz. We use 14 bit ADC's at 500 MSPS to give very good dynamic range, with a noise floor below 100 dBV. At 10 MHz, Sinad is >60 dB, THD<-76 dBc and HD2+3<-80 dBc. Phase variation between channels is better than +/-160ps (on the same range).
With the CS548 you can view the high side gate drive in a power switch as it is switching. Our CS1090 is designed to show this with FET switches that switch between 0 and 500V in about 10ns. The high side gate drive is therefore slewing at 50 kV/us. Here is the connection:
Using the Cleverscope4 application we can measure 4 channels (with one CS448) or 8 channels (with two CS448's trigger and clock linked) of isolated signals. This is the measured result from the CS1090 HV bridge:
The gates are slewing 0->500V in about 10ns while the measurement is made. Dead time is about 1.077us (Markers 1-2).
and then if we zoom in we can look at the transition itself:
Here we see the Miller Plateau lasts about 27.5 ns. The gate is being driven with 10 ohm from 12.5V, and the gate voltage is about 6.4V. So the gate charge is (12.5-6.4)/10 x 22.5n = 13.7 nC. The FET turn on delay is about 11 ns. We see a switch rise time of about 10ns.
We were also at APEC and PCIM this year (2019), and demonstrated using two Cree SicFET half bridges. This is the full setup:
and here is a zoom on the demo system so you can see the labels:.
This setup is described in CS448 PCIM 2019 -measuring a Cree SicFET full bridge...
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